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Integrated Circuit Systems, Inc.
ICS9250-27
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E and 815 type chipset. Output Features: * 3 CPU (2.5V) (up to 133MHz achievable through I2C) * 9 SDRAM (3.3V) (up to 133MHz achievable through I2C) * 7 PCI (3.3 V) @33.3MHz * 2 IOAPIC (2.5V) @ 33.3 MHz * 3 Hublink clocks (3.3 V) @ 66.6 MHz * 2 (3.3V) @ 48 MHz (Non spread spectrum) * 1 REF (3.3V) @ 14.318 MHz Features: * Supports spread spectrum modulation, 0 to -0.5% down spread. * I2C support for power management * Efficient power management scheme through PD# * Uses external 14.138 MHz crystal * Alternate frequency selections available through I2C control.
Pin Configuration
*FS2//REF0 VDD X1 X2 GND GND 3V66-0 3V66-1 3V66-2 VDD VDD PCICLK_F PCICLK0 GND PCICLK1 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 VDD VDD GND GND 48MHz_0 48MHz_1 VDD FS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND IOAPIC0 IOAPIC1 VDDL CPUCLK0 VDDL0 CPUCLK1 CPUCLK2 GNDL GND SDRAM0 SDRAM1 VDD SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD SDRAM6 SDRAM7 GND SDRAM_F VDD PD# SCLK SDATA FS1
56-Pin 300mil SSOP
* This input has a 50K pull-down to GND.
Block Diagram Functionality
X1 X2 XTAL OSC PLL1 Spread Spectrum /2 /3
3
REF0
FS2 X X
FS1 0 0 1 1 1 1
FS0 0 1 0 1 0 1
ICS9250-27
Function Tristate Test Active CPU = 66MHz SDRAM = 100MHz Active CPU = 100MHz SDRAM = 100MHz Active CPU = 133MHz SDRAM = 133MHz Active CPU = 133MHz SDRAM = 100MHz
VDDL CPU66/100/133 (2:0) 3V66 (2:0) SDRAM (7:0) SDRAM_F
0 0 1 1
FS (2:0) PD#
Control Logic
3 8
SDATA SCLK Config Reg
/2
6
PCICLK (5:0) PCICLK_F
/2 PLL2
2
IOAPIC (1:0) VDDL 48MHz (1:0)
Power Groups
AVDD = Pin 22 Analog power for PLL AGND = Pin 23 Analog ground VDD48 = Pin 27 Analog power for 48MHz PLL GND = Pin 24 Analog ground for 48MHz PLL
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2
9250-27 Rev B 02/15/01 Third party brands and names are the property of their respective owners.
ICS9250-27
General Description
The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS925027 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER 1 3 4 5, 6, 14, 17, 23, 24, 35, 41, 47, 48, 56 9, 8, 7 P I N NA M E FS2 REF0 X1 X2 GND 3V66 (2:0) TYPE IN OUT IN OUT PWR OUT PWR OUT OUT OUT OUT IN I/O IN IN OUT OUT OUT PWR OUT DESCRIPTION Function Select pin. Determines CPU frequency, all output functionality 3.3V, 14.318MHz reference clock output. Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V power supply Free running 3.3V PCI clock output 3.3V PCI clock outputs 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B 3.3V fixed 48MHz clock output. Stronger output for graphics/video i n t e r fa c e ( m i n i m u m 1 V / n s e d g e r a t e ) Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C 3.3V free running 100MHz SDRAM, cannot be turned off through I2C 2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending on FS pins. 2.5V power suypply for CPU & IOAPIC 2.5V clock outputs running at 33.3MHz.
2, 10, 11, 21, VDD 22, 27, 33, 38, 44 12 20, 19, 18, 16, 15, 13 25 26 29, 28 30 31 32 36, 37, 39, 40, 42, 43, 45, 46 34 49, 50, 52 51, 53 54, 55 PCICLK_F PCICLK (5:0) 48MHz_0 48MHz_1 FS (1:0) SDATA SCLK PD# SDRAM (7:0) SDRAM_F CPUCLK (2:0) VDDL IOAPIC (1:0)
2
ICS9250-27
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
Maximum Allowed Current
815 Condition Powerdown Mode (PWRDWN# = 0 Full Active 66MHz FS[2:0] = 010 Full Active 100MHz FS[2:0] = 011 Full Active 133MHz FS[2:0] = 111 Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND 10mA 70mA 100mA Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND 10mA 280mA 280mA
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 66MHz LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OFF ON VCOs OFF ON
3
ICS9250-27
Truth Table
FS2 X X 0 0 1 1 FS1 0 0 1 1 1 1 FS0 0 1 0 1 0 1 CPU Tristate TCLK/2 66.6 MHz 100 MHz 133 MHz 133 MHz SDRAM Tristate TCLK/2 100 MHz 100 MHz 133 MHz 100 MHz 3V66 Tristate TCLK/3 66.6 MHz 66.6 MHz 66.6 MHz 66.6 MHz PCI Tristate TCLK/6 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz 48MHz Tristate TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz REF Tristate TCLK 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz IOAPIC Tristate TCLK/6 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz
Byte 0: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
26 25 49
Name Reserved ID Reserved ID Reserved ID Reserved ID SpreadSpectrum (1=On/0=Off) 48MHz 1 48MHz 0 CPUCLK2
PWD 0 0 0 0 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 36 37 39 40 42 43 45 46
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
PWD 1 1 1 1 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
4
ICS9250-27
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 9 20 19 18 16 15 13 -
Name 3V66-2 (AGP) PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Undefined bit
PWD 1 1 1 1 1 1 1 X
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 3. Undefined bit can be wirtten with either a "1" or "0". Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ICS Reserved bit (Note 2) ICS Reserved bit (Note 2) ICS Reserved bit (Note 2) ICS Reserved bit (Note 2) ICS Reserved bit (Note 2) Undefined bit (Note 3) Undefined bit (Note 3) Bit 0 0 0 0 Bit 0 0 1 1 1 1 FS0 0 1 0 1 0 1 0 1 FS1 0 0 1 1 0 0 1 1
Desctiption
PWD 0 0 0 0 0 X X
CPUCLK SDRAM MHz MHz 66.66 100.0 133.32 133.32 66.66 100.0 133.32 133.32 100.0 100.0 133.32 100.0 100.0 100.0 133.32 133.32
3V66 MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66
PCICLK IOAPIC MHz MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 0 Note 1
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free during this transition, and only SDRAM will change. Note 2: "ICS RESERVED BITS" must be writtern as "O". Note3: Undefined bits can be written either as "1 or 0"
5
ICS9250-27
Byte 4: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 5: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
Group Timing Relationship Table1
Group CPU 66MHz SDRAM 100MHz Offset CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI IOAPIC to PCI USB & DOT 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps N/A 1.0ns N/A CPU 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps N/A 1.0ns N/A CPU 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps N/A 1.0ns N/A CPU 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns 3.75ns 1.5 -3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps N/A 1.0ns N/A
6
ICS9250-27
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage VIH 2 VSS-0.3 Input Low Voltage VIL VIN = VDD -5 Input High Current IIH VIN = 0 V; Inputs with no pull-up resistors -5 2 IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors -200 -100 IIL2 97 CL = 0 pF; Select @ 66 MHz 91 CL = 0 pF; Select @ 100 MHz 100 CL = 0 pF; Select @ 133 MHz IDD3.3OP 295 CL = Max loads; Select @ 66 MHz 280 CL = Max loads; Select @ 100 MHz Operating Supply Current CL = Max loads; Select @ 133 MHz CL = 0 pF; Select @ 66 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz CL = Max loads; Select @ 66 MHz CL = Max loads; Select @ 100 MHz CL = Max loads; Select @ 133 MHz CL = Max loads Input address VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 1 1 12 300 16 25 26 19 34 40 220 <1 14.318 7 6 27 45 5 5 5 10 10 MAX VDD+0.3 0.8 5 UNITS V V A A 115 110 165 330 320 395 19 35 40 30 50 70 400 10 16 5 mA
mA
mA
IDD2.5OP
mA
Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Transition time
1 1
IDD3.3PD IDD.25PD Fi Lpin CIN COUT CINX Ttrans Ts TSTAB tPZH,tPZL tPHZ,tPLZ
A MHz nH pF pF pF ms ms ms ns ns
Settling time Clk Stabilization1 Delay1
1
Guaranteed by design, not 100% tested in production.
7
ICS9250-27
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1
MIN 13.5 13.5 2 -27 27 0.4 0.4 45 45
TYP 22 23
MAX UNITS 45 45 0.4 V V mA mA ns ns % ps ps
RDSP2B
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, 66, 100 MHz VT = 1.25 V, 133 MHz VT = 1.25 V VT = 1.25 V
RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B tsk2B
-68 -9 54 11 1.1 1.1 50 53 118 148
-27 30 1.6 1.6 55 55 175 250
Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1
1
tjcyc-cyc2B
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1 1
MIN 12 12 2.4 -33 30 0.4 0.4 45
TYP 17 18
MAX UNITS 55 55 0.55 V V mA mA ns ns % ps ps
RDSP1
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1
-108 -9 95 29 1.2 1.3 50 82 123
-33 38 1.8 1.8 55 175 500
tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
8
ICS9250-27
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
MIN 9 9 2 -27 27 0.4 0.4 45
TYP 21.5 23
MAX UNITS 30 30 0.4 V V mA mA ns ns % ps
RDSP4B
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
RDSN4B VOH4B VOL4B IOH4B IOL4B tr4B tf4B dt4B
-68 -9 54 11 1.1 1.1 50 123
-27 30 1.6 1.6 55 500
Duty Cycle Jitter, Cycle-to-cycle1
1
tjcyc-cyc4B
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP 14 18
MAX UNITS 24 24 0.4 V V mA mA ns ns % ps ps
RDSP3
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 2.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, 66, 100 MHz
RDSN3 VOH3 VOL3 IOH3 IOL3 tr3 tf3 dt3 tsk3
-92 -16 68 29 1 1.5 52 164 180
-46 53 1.6 1.6 55 250 250
Duty Cycle Skew window1 Jitter, Cycle-to-cycle
1 1
tjcyc-cyc3
Guaranteed by design, not 100% tested in production.
9
ICS9250-27
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1 1
MIN 12 12 2.4 -33 30 0.4 0.4 45
TYP 14 18
MAX UNITS 55 55 0.55 V V mA mA ns ns % ps ps
RDSP1
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1
-106 -14 94 29 1.3 1.4 52 304 170
-33 38 2 2 55 500 500
tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
MIN 20 20 2.4 -29 29 0.4 0.4 45
TYP 32.6 31
MAX UNITS 60 60 0.55 V V mA mA ns ns % ps ps
RDSP5
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks
RDSN5 VOH15 VOL5 IOH5 IOL5 tr5 tf5 dt5
-54 -11 54 16 1.4 1.7 53 215 930
-23 27 4 4 55 500 1000
Duty Cycle Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1
1
tjcyc-cyc5 tjcyc-cyc5
Guaranteed by design, not 100% tested in production.
10
ICS9250-27
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP 16.7 18.4
MAX UNITS 24 24 0.55 V V mA mA ns ns % ps ps
RDSP3
1 1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 2.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
RDSN3 VOH3 VOL3 IOH3 IOL3 tr3 tf3 dt3 tsk3
-82 -20 95 28 1.1 1.1 51 116 196
-46 53 1.6 1.6 55 250 500
Duty Cycle Skew Jitter, Cycle-to-cycle1
1
tjcyc-cyc3B
Guaranteed by design, not 100% tested in production.
11
ICS9250-27
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.3V 66MHz PCI 33MHz IOAPIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
12
ICS9250-27
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9250-27
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MA X .380 .455 .630 .730 .830
6/ 1/ 00 REV B
J EDEC M O- 118 DOC# 10- 0034
Ordering Information
ICS9250yF-27-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
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Price & Availability of ICS9250-27

	To Download ICS9250-27 Datasheet File
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